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// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// File name : cpm_reg.h
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// Version : V0.1
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// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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#ifndef __CPM_REG_H__
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#define __CPM_REG_H__
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#include "type.h"
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#define INTERNAL_CLK_SEL 0
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#define EXTERNAL_CLK_SEL 1
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typedef struct
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{
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__IO unsigned int CPM_SLPCFGR;//0x00
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__IO unsigned int CPM_SLPCR;//0x04
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__IO unsigned int CPM_SCDIVR;//0x08
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__IO unsigned int CPM_PCDIVR1;//0x0c
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__IO unsigned int CPM_PCDIVR2;//0x10
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__IO unsigned int CPM_PCDIVR3;//0x14
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__IO unsigned int CPM_CDIVUPDR;//0x18
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__IO unsigned int CPM_CDIVENR;//0x1c
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__IO unsigned int CPM_OCSR;//0x20
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__IO unsigned int CPM_CSWCFGR;//0x24
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__IO unsigned int CPM_CTICKR;//0x28
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__IO unsigned int CPM_CHIPCFGR;//0x2c
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__IO unsigned int CPM_PWRCR;//0x30
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__IO unsigned int CPM_SLPCNTR;//0x34
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__IO unsigned int CPM_WKPCNTR;//0x38
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__IO unsigned int CPM_MULTICGTCR;//0x3c
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__IO unsigned int CPM_SYSCGTCR;//0x40
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__IO unsigned int CPM_AHB3CGTCR;//0x44
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__IO unsigned int CPM_ARITHCGTCR;//0x48
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__IO unsigned int CPM_IPSCGTCR;//0x4c
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__IO unsigned int CPM_VCCGTRIMR;//0x50
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__IO unsigned int CPM_VCCLTRIMR;//0x54
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__IO unsigned int CPM_VCCVTRIMR;//0x58
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__IO unsigned int CPM_VCCCTMR;//0x5c
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__IO unsigned int CPM_O8MTRIMR;//0x60
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unsigned int RESERVED1;//0x64
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__IO unsigned int CPM_O600MTRIMR;//0x68
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__IO unsigned int CPM_CARDTRIMR;//0x6c
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__IO unsigned int CPM_OSCLSTIMER;//0x70
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__IO unsigned int CPM_OSCHSTIMER;//0x74
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__IO unsigned int CPM_OSCESTIMER;//0x78
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__IO unsigned int CPM_PWRSR;//0x7c
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unsigned int RESERVED2[3];//0x80~0x88
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__IO unsigned int CPM_RTCTRIMR;//0x8c
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__IO unsigned int CPM_PADWKINTCR;//0x90
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__IO unsigned int CPM_FILTCNTR;//0x94
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__IO unsigned int CPM_CARDPOCR;//0x98
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__IO unsigned int CPM_RTCSTIMER;//0x9c
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__IO unsigned int CPM_MPDSLPCR;//0xa0
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__IO unsigned int CPM_MRMCR;//0xa4
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unsigned int RESERVED3;//0xa8
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__IO unsigned int CPM_MULTIRSTCR;//0xac
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__IO unsigned int CPM_SYSRSTCR;//0xb0
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__IO unsigned int CPM_AHB2RSTCR;//0xb4
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__IO unsigned int CPM_ARITHRSTTCR;//0xb8
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__IO unsigned int CPM_IPRSTCR;//0xbc
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__IO unsigned int CPM_SLPCFGR2;//0xc0
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unsigned int RESERVED4[3];//0xc4~0xcc
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__IO unsigned int CPM_PDNCNTR;//0xd0
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__IO unsigned int CPM_PONCNTR;//0xd4
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}CPM_TypeDef;
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//----------------------
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// CPM BIT DEFINE
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//----------------------
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/* CPM_SCDIVR */
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#define SYS_DIV_MASK (0xff)
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#define TRACE_DIV_MASK (0xff00)
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#define CLKOUT_DIV_MASK (0xff0000)
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#define SYS_DIV_SHIFT (0)
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#define TRACE_DIV_SHIFT (8)
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#define CLKOUT_DIV_SHIFT (16)
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/*CPM_PCDIVER1 MACRO*/
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#define IPS_DIV_MASK (0xf)
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#define AHB3_DIV_MASK (0xf00)
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#define ARITH_DIV_MASK (0xf000)
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#define SDRAM_DIV_MASK (0xf0000)
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#define SDRAM_SM_MASK (0x7000000)
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#define SDRAM2LCD_DIV_MASK (0xf0000000)
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#define IPS_DIV_SHIFT (0)
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#define AHB3_DIV_SHIFT (8)
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#define ARITH_DIV_SHIFT (12)
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#define SDRAM_DIV_SHIFT (16)
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#define SDRAM_SM_SHIFT (24)
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#define SDRAM2LCD_DIV_SHIFT (28)
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/*CPM_PCDIVER2 MACRO*/
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#define MCC_DIV_MASK (0x1ff)
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#define MCCADR_DIV_MASK (0xe00)
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#define ADC_DIV_MASK (0xf000)
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#define CLCD_DIV_MASK (0xf0000)
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#define MESH_DIV_MASK (0xf000000)
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#define TC_DIV_MASK (0xf0000000)
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#define MCC_DIV_SHIFT (0)
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#define MCCADR_DIV_SHIFT (9)
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#define ADC_DIV_SHIFT (12)
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#define CLCD_DIV_SHIFT (16)
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#define MESH_DIV_SHIFT (24)
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#define TC_DIV_SHIFT (28)
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/*CPM_PCDIVER3 MACRO*/
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#define DMA2D_SRAM_DIV_MASK (0xf)
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#define MIPI_SAMPLE_DIV_MASK (0xf0)
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#define DCMI_PIX_DIV_MASK (0xf00)
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#define DCMI_SENSOR_DIV_MASK (0x3f0000)
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#define DMA2D_SRAM_DIV_SHIFT (0)
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#define MIPI_SAMPLE_DIV_SHIFT (4)
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#define DCMI_PIX_DIV_SHIFT (8)
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#define DCMI_SENSOR_DIV_SHIFT (16)
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/*CPM_CDIVUPDR MACRO*/
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#define PERDIV_UPD (1)
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#define SYSDIV_UPD (2)
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/*CPM_CDIVENR MACRO*/
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#define IPS_DIVEN (1<<0)
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#define AHB3_DIVEN (1<<2)
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#define ARITH_DIVEN (1<<3)
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#define SDRAM_DIVEN (1<<4)
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#define SDRAM_SM_DIVEN (1<<6)
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#define SDRAM2LCD_DIVEN (1<<7)
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#define MCC_DIVEN (1<<8)
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#define ADC_DIVEN (1<<10)
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#define CLCD_DIVEN (1<<11)
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#define MESH_DIVEN (1<<12)
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#define TC_DIVEN (1<<13)
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#define TRACE_DIVEN (1<<14)
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#define CLKOUT_DIVEN (1<<15)
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#define DMA2D_SRAM_DIVEN (1<<16)
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#define MIPI_SAMPLE_DIVEN (1<<17)
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#define DCMI_PIX_DIVEN (1<<18)
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#define DCMI_SENSOR_DIVEN (1<<19)
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/*CPM_OCSR MACRO*/
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#define OSC8M_EN (1<<0)
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#define PMU128K_EN (1<<1)
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#define USB_PHY240M_EN (1<<2)
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#define OSC160M_EN (1<<3)
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#define OSCEXT_EN (1<<4)
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#define RTC32K_EN (1<<5)
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#define OSC8M_STABLE (1<<8)
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#define PMU128K_STABLE (1<<9)
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#define USB_PHY240M_STABLE (1<<10)
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#define OSC160M_STABLE (1<<11)
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#define OSCEXT_STABLE (1<<12)
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#define RTC32K_STABLE (1<<13)
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#define PMU2K_VALID (1<<14)
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#define TRNG_OSCEN_MASK (0xf000000)
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#define TRNG_OSCEN_SHIFT (24)
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/* CPM_CSWCFGR MACRO*/
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#define SYSCLK_SEL_MASK (0x3)
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#define DCMI_SENSOR_SEL_MASK (0x3f)
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#define OSCL_SEL (1<<6)
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#define OSCH_SEL (1<<7)
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#define SYS_SEL_ST_MASK (0xf00)
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#define DCMI_SENSOR_SEL_ST_MASK (0x70000)
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#define OSCL_SEL_ST_MASK (0x300000)
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#define OSCH_SEL_ST_MASK (0xc00000)
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#define CLKOUT_SEL_MASK (0x3000000)
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#define CLKOUT_SEL_ST_MASK (0xf0000000)
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#define SYS_SEL_SHIFT (0)
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#define DCMI_SENSOR_SEL_SHIFT (4)
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#define SYS_SEL_ST_SHIFT (8)
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#define DCMI_SENSOR_SEL_ST_SHIFT (16)
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#define OSCL_SEL_ST_SHIFT (20)
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#define OSCH_SEL_ST_SHIFT (22)
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#define CLKOUT_SEL_SHIFT (24)
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#define CLKOUT_SEL_ST_SHIFT (28)
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#define SYSCLK_SEL_OSC8M (0x00)
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#define SYSCLK_SEL_OSC160M (0x01)
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#define SYSCLK_SEL_USBPHY240M (0x02)
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#define SYSCLK_SEL_OSCEXT (0x03)
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#define CLKSEL_ST_OSC8M (0x0100)
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#define CLKSEL_ST_OSC160M (0x0200)
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#define CLKSEL_ST_USBPHY240M (0x0400)
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#define CLKSEL_ST_OSCEXT (0x0800)
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/* CPM_SRSTCR1 */
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#define USBC_RST_RELEASE_BIT (1<<8)
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#define USBPHY_RST_RELEASE_BIT (1<<13)
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#define PWRCR_PHY_PSWEN_BIT (1<<24)
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#define PWRCR_PHY_RSTMASK_BIT (1<<25)
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#define PWRCR_PHY_O_ISOEN_BIT (1<<26)
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#define PWRCR_PHY_I_ISOEN_BIT (1<<27)
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#define USBPHY_PLL_SRM (1<<28)
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#define USBPHY_CFG_SRM (1<<29)
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#endif /* __CPM_REG_H__ */
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