|
|
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
// File name : memmap.h
|
|
|
// Version : V0.1
|
|
|
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
|
#ifndef __MEMMAP_H__
|
|
|
#define __MEMMAP_H__
|
|
|
|
|
|
|
|
|
#define IOCTRL_BASE_ADDR (0x40000000)
|
|
|
#define CCM_BASE_ADDR (0x40001000)
|
|
|
#define RESET_BASE_ADDR (0x40002000)
|
|
|
#define EFM_BASE_ADDR (0x40003800)
|
|
|
#define CPM_BASE_ADDR (0x40004000)
|
|
|
#define WDT_BASE_ADDR (0x40005000)
|
|
|
#define TC_BASE_ADDR (0x40006000)
|
|
|
#define PIT1_BASE_ADDR (0x40007000)
|
|
|
#define PIT2_BASE_ADDR (0x40008000)
|
|
|
#define USI1_BASE_ADDR (0x40009000)
|
|
|
#define EDMAC_BASE_ADDR (0x4000a000)
|
|
|
#define SPI1_BASE_ADDR (0x40010000)
|
|
|
#define SPI2_BASE_ADDR (0x40011000)
|
|
|
#define SPI3_BASE_ADDR (0x40012000)
|
|
|
#define SCI1_BASE_ADDR (0x40013000)
|
|
|
#define SCI2_BASE_ADDR (0x40014000)
|
|
|
#define USI2_BASE_ADDR (0x40015000)
|
|
|
#define I2C1_BASE_ADDR (0x40017000)
|
|
|
#define PWM_BASE_ADDR (0x40018000)
|
|
|
#define EPORT_BASE_ADDR (0x40019000)
|
|
|
#define EPORT1_BASE_ADDR (0x4001a000)
|
|
|
#define I2C2_BASE_ADDR (0x4001b000)
|
|
|
#define I2C3_BASE_ADDR (0x4001c000)
|
|
|
#define SCI3_BASE_ADDR (0x4001d000)
|
|
|
#define ADC_BASE_ADDR (0x40020000)
|
|
|
#define DAC_BASE_ADDR (0x40021000)
|
|
|
#define MCC_BASE_ADDR (0x40022000)
|
|
|
#define TSI_BASE_ADDR (0x40023000)
|
|
|
#define EPORT2_BASE_ADDR (0x40024000)
|
|
|
#define EPORT3_BASE_ADDR (0x40025000)
|
|
|
#define EPORT4_BASE_ADDR (0x40026000)
|
|
|
#define LD_BASE_ADDR (0x40030000)
|
|
|
#define TRNG_BASE_ADDR (0x40031000)
|
|
|
#define PGD_BASE_ADDR (0x40032000)
|
|
|
#define SECDET_BASE_ADDR (0x40033000)
|
|
|
#define PCI_BASE_ADDR (0x40034000)
|
|
|
#define PMURTC_BASE_ADDR (0x40035000)
|
|
|
#define SM1_BASE_ADDR (0x40036000)
|
|
|
#define CRYPTO_BASE_ADDR (0x40037000)
|
|
|
#define SHA_BASE_ADDR (0x40038000)
|
|
|
#define EDMAC0_BASE_ADDR (0x40039000)
|
|
|
#define SSF33_BASE_ADDR (0x4003a000)
|
|
|
#define DES_BASE_ADDR (0x40040000)
|
|
|
#define AES_BASE_ADDR (0x40041000)
|
|
|
#define SM4_BASE_ADDR (0x40042000)
|
|
|
#define ZUC_BASE_ADDR (0x40043000)
|
|
|
#define CRC0_BASE_ADDR (0x40044000)
|
|
|
#define CRC1_BASE_ADDR (0x40045000)
|
|
|
#define DMA1_BASE_ADDR (0x40046000)
|
|
|
#define DMA2_BASE_ADDR (0x40047000)
|
|
|
#define SPIM2_BASE_ADDR (0x4004a000)
|
|
|
#define USBC_BASE_ADDR (0x4004c000)
|
|
|
#define CACHE_BASE_ADDR (0x40051000)
|
|
|
#define CACHE2_BASE_ADDR (0x40055000)
|
|
|
#define SPIM1_BASE_ADDR (0x60000000)
|
|
|
#define M4_BASE_ADDR (0xe0000000)
|
|
|
#endif /* __MEMMAP_H__ */
|
