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// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// File name : ssi_reg.h
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// Version : V0.1
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// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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#ifndef __SSI_REG_H__
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#define __SSI_REG_H__
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#include "type.h"
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typedef struct
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{
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__IO unsigned int SSI_CTRLR0; //0x00
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__IO unsigned int SSI_CTRLR1; //0x04
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__IO unsigned int SSI_SSIENR; //0x08
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__IO unsigned int SSI_MWCR; //0x0c
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__IO unsigned int SSI_SER; //0x10
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__IO unsigned int SSI_BAUDR; //0x14
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__IO unsigned int SSI_TXFTLR; //0x18
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__IO unsigned int SSI_RXFTLR; //0x1c
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__IO unsigned int SSI_TXFLR; //0x20
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__IO unsigned int SSI_RXFLR; //0x24
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__IO unsigned int SSI_SR; //0x28
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__IO unsigned int SSI_IMR; //0x2c
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__IO unsigned int SSI_ISR; //0x30
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__IO unsigned int SSI_RISR; //0x34
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__IO unsigned int SSI_TXOICR; //0x38
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__IO unsigned int SSI_RXOICR; //0x3c
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__IO unsigned int SSI_RXUICR; //0x40
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__IO unsigned int SSI_MSTICR; //0x44
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__IO unsigned int SSI_ICR; //0x48
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__IO unsigned int SSI_DMACR; //0x4c
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__IO unsigned int SSI_DMATDLR; //0x50
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__IO unsigned int SSI_DMARDLR; //0x54
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__IO unsigned int SSI_IDR; //0x58
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__IO unsigned int SSI_SSIC_VERSION_ID; //0x5c
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__IO unsigned int SSI_DR; //0x60
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__IO unsigned int RESERVERED[35];
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__IO unsigned int SSI_RX_SAMPLE_DELAY; //0xf0
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__IO unsigned int SSI_SPI_CTRLR0; //0xf4
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__IO unsigned int SSI_DDR_DRIVE_EDGE; //0xf8
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__IO unsigned int SSI_XIP_MODE_BITS; //0xfc
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__IO unsigned int XIP_INCR_INST; //0x100
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__IO unsigned int XIP_WRAP_INST; //0x104
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__IO unsigned int XIP_CTRL; //0x108
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__IO unsigned int XIP_SER; //0x10C
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__IO unsigned int XRXOICR; //0x110
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__IO unsigned int XIP_CNT_TIME_OUT; //0x114
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}SSI_TypeDef;
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#define SSI1 (SSI_TypeDef *)(0x60000000)
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#define SSI2 (SSI_TypeDef *)(0x4004a000)
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#define SR_TXE 0x20
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#define SR_RFF 0x10
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#define SR_RFNE 0x08
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#define SR_TFE 0x04
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#define SR_TFNF 0x02
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#define SR_BUSY 0x01
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#define DMACR_TDMAE 0x02
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#define DMACR_RDMAE 0x01
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//SSI_CTRLR0
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#define CTRLR0_DFS_VALUE(x) (x<<0)
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#define CTRLR0_FRF_MOT (0x00<<6)
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#define CTRLR0_TMOD_VALUE(x) (x<<10)
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#define CTRLR0_TMOD_TX_AND_RX (0x00<<10)
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#define CTRLR0_TMOD_TX_ONLY (0x01<<10)
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#define CTRLR0_TMOD_RX_ONLY (0x02<<10)
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#define CTRLR0_TMOD_EEPROM_READ (0x03<<10)
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#define CTRLR0_CFS_VALUE(x) (x<<16)
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#define CTRLR0_SCPH_MASK (1<<8)
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#define CTRLR0_SCPOL_MASK (1<<9)
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#define CTRLR0_SRL_MASK (1<<13)
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#define CTRLR0_SSTE_MASK (1<<14)
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#define CTRLR0_SPI_FRF_STD (0x00<<22)
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#define CTRLR0_SPI_FRF_DUAL (0x01<<22)
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#define CTRLR0_SPI_FRF_QUAD (0x02<<22)
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//SPI_CTRLR0
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#define CTRLR0_TRANS_TYPE_TT0 (0x00<<0) //Instruction and Address STD mode
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#define CTRLR0_TRANS_TYPE_TT1 (0x01<<0) //Instruction STD mode and Address CTRLR0.SPI_FRF mode
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#define CTRLR0_TRANS_TYPE_TT2 (0x02<<0) //Instruction and Address CTRLR0.SPI_FRF mode
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#define CTRLR0_ADDR_L_VALUE(x) (x<<2)
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#define CTRLR0_INST_L_VALUE(x) (x<<8)
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#define CTRLR0_WAIT_CYCLES_VALUE(x) (x<<11)
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#define CTRLR0_CLK_STRETCH_EN_MASK (1<<30)
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#endif /* __SSI_REG_H__ */
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