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/**
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******************************************************************************
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* @file LT7689_C.h
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* @author MCD Application Team
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* @version V2.4.2
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* @date 13-November-2015
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* @brief CMSIS LT7689 Device Peripheral Access Layer Header File.
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*
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* This file contains:
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* - Data structures and the address mapping for all peripherals
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* - Peripheral's registers declarations and bits definition
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* - Macros to access peripheral’s registers hardware
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2018 C*core</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of C*core nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS_Device
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* @{
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*/
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/** @addtogroup LT7689
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* @{
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*/
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#ifndef __LT7689_C_H
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#define __LT7689_C_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Configuration_section_for_CMSIS
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* @{
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*/
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/**
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* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
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*/
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#define __CM4_REV 0x0001 /*!< Core revision r0p1*/
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#define __MPU_PRESENT 1 /*!< LT7689 provides an MPU*/
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#define __NVIC_PRIO_BITS 4 /*!< LT7689 uses 4 Bits for the Priority Levels*/
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used*/
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#define __FPU_PRESENT 1 /*!< FPU present*/
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/**
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* @}
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*/
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/** @addtogroup Peripheral_interrupt_number_definition
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* @{
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*/
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/**
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* @brief LT7689 Interrupt Number Definition, according to the selected device
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* in @ref Library_configuration_section
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*/
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typedef enum
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{
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/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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/****** LT7689 specific Interrupt Numbers *******************************************************************/
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EFM_IRQn = 0, /*!< EFM Interrupt */
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PMU_IRQn = 1, /*!< PMU Interrupt */
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TC_IRQn = 2, /*!< TC Interrupt */
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PIT1_IRQn = 3, /*!< PIT1 interrupt */
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PIT2_IRQn = 4, /*!< PIT2 Interrupt */
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ENCR_IRQn = 5, /*!< ENCR Interrupt */
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ENCR1_IRQn = 6, /*!< ENCR1 Interrupt */
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DMA1_IRQn = 7, /*!< DMA Interrupt */
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DMA2_IRQn = 8, /*!< DMA2 Interrupt */
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DMA2D_IRQn = 9, /*!< DMA2D Interrupt */
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TRNG_IRQn = 10, /*!< TRNG Interrupt */
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SEC_PGD_LD_FD_IRQn = 11, /*!< SEC_DET/PGD/LD/FD Interrupt */
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PCI_DET_IRQn = 12, /*!< PCI_DET Interrupt */
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ASYNC_TIMER_IRQn = 13, /*!< ASYNC TIMER Interrupt */
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PCI_IRQn = 14, /*!< PCI Interrupt */
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PMU_RTC_IRQn = 15, /*!< PMU RTC Interrupt */
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RSA_IRQn = 16, /*!< RSA Interrupt */
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SHA_IRQn = 17, /*!< SHA Interrupt */
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AES_IRQn = 18, /*!< AES Interrupts */
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SMS4_IRQn = 19, /*!< SMS4 Interrupt */
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QADC_IRQn = 20, /*!< QADC Interrupt */
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DAC_IRQn = 21, /*!< DAC Interrupt */
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MCC_IRQn = 22, /*!< MCC Interrupt */
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TSI_IRQn = 23, /*!< TSI Interrupts */
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USBC_IRQn = 24, /*!< USBC interrupt */
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MIPI_IRQn = 25, /*!< MIPI interrupt */
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SPI1_IRQn = 26, /*!< SPI1 interrupt */
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SPI2_IRQn = 27, /*!< SPI2 Interrupt */
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SPI3_IRQn = 28, /*!< SPI3 Interrupt */
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SPIM1_IRQn = 29, /*!< SPIM1 Interrupt */
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SPIM2_IRQn = 30, /*!< SPIM2 global Interrupt */
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SPIM3_EV_IRQn = 31, /*!< SPIM3 Event Interrupt */
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SCI1_IRQn = 32, /*!< SCI1 Interrupt */
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SCI2_IRQn = 33, /*!< SCI2 Interrupt */
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USI2_IRQn = 34, /*!< USI2 Error Interrupt */
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// USI3_IRQn = 35, /*!< USI2 global Interrupt */
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I2C_1_IRQn = 36, /*!< I2C global Interrupt */
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PWM0_IRQn = 37, /*!< PWM0 Interrupt */
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PWM1_IRQn = 38, /*!< PWM1 Interrupt */
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PWM2_IRQn = 39, /*!< PWM2 Interrupt */
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PWM3_IRQn = 40, /*!< PWM3 Interrupts */
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EPORT0_0_IRQn = 41, /*!< EPORT0_0 Interrupt */
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EPORT0_1_IRQn = 42, /*!< EPORT0_1 interrupt */
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EPORT0_2_IRQn = 43, /*!< EPORT0_2 interrupt */
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EPORT0_3_IRQn = 44, /*!< EPORT0_3 interrupt */
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EPORT0_4_IRQn = 45, /*!< EPORT0_4 interrupt */
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EPORT0_5_IRQn = 46, /*!< EPORT0_5 Interrupt */
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EPORT0_6_IRQn = 47, /*!< EPORT0_6 Interrupt */
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EPORT0_7_IRQn = 48, /*!< EPORT0_7 Interrupt */
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EPORT1_0_IRQn = 49, /*!< EPORT1_0 Interrupt */
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EPORT1_1_IRQn = 50, /*!< EPORT1_1 Interrupt */
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EPORT1_2_IRQn = 51, /*!< EPORT1_2 Interrupt */
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EPORT1_3_IRQn = 52, /*!< EPORT1_3 Interrupt */
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EPORT1_4_IRQn = 53, /*!< EPORT1_4 Interrupt */
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EPORT1_5_IRQn = 54, /*!< EPORT1_5 interrupts */
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EPORT1_6_IRQn = 55, /*!< EPORT1_6 interrupt */
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EPORT1_7_IRQn = 56, /*!< EPORT1_7 Interrupt */
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CLCD_IRQn = 57, /*!< CLCD Interrupt */
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DCMI_IRQn = 58, /*!< DCMI Interrupt */
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I2C_2_IRQn = 59, /*!< I2C Interrupt */
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I2C_3_IRQn = 60, /*!< I2C Interrupt */
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SCI3_IRQn = 61, /*!< SCI3 Interrupt */
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// SCI4_IRQn = 62, /*!< SCI4 Interrupt */
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RESERVED = 62,
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USI1_IRQn = 63, /*!< USI1 Interrupt */
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} IRQn_Type;
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/**
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* @}
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*/
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#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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#include "system_lt7689.h"
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#include <stdint.h>
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/**
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* @brief Debug MCU
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*/
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typedef struct
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{
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__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
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__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
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__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
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__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
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}DBGMCU_TypeDef;
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/**
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* @}
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*/
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/** @addtogroup Peripheral_memory_map
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* @{
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*/
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#define ROM_BASE ((uint32_t)0x00000000) /*!< ROM(64K Bytes) base address in the alias region*/
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#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(1.25 MB) base address in the alias region*/
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#define SYS_SRAM_BASE ((uint32_t)0x10000000) /*!< SYSTEM SRAM base address in the alias region*/
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#define IN_SRAM_BASE ((uint32_t)0x20000000) /*!< Internal SRAM in the alias region*/
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#define SDRAM_BASE ((uint32_t)0x60000000) /*!< SDRAM base address in the alias region*/
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#define REG_BASE ((uint32_t)0x40000000) /*!< peripherals registers base address*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __LT7689_H */
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/************************ (C) COPYRIGHT C*core *****END OF FILE****/
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