#include "OTA_H.h"

#include "eflash_drv.h"

#include "uart.h"

#include "bsp.h"

#include "pit.h"

#include "pit32_drv.h"

#include "ioctrl_drv.h"

#include "usb_drv.h"

#include "usb_const.h"

#include "meg.h" 

/****************test************************/

extern unsigned int number ;

unsigned int ota_lt7689(unsigned char * updata_p,unsigned int length , unsigned int flash_addr)

{

				EFLASH_Init(g_sys_clk/1000);

				EFLASH_SetWritePermission();

				EFLASH_Write(flash_addr,updata_p,length);

				EFLASH_ClrWritePermission();

				return 0;

}

unsigned int ota_ui(unsigned int addr , unsigned char * ota_lt_buf , unsigned int length)

{

		for(unsigned char i=0;i<1;i++)

		{

//			pWrBuf = &(vcom_buf[id][i*2048]);                  

//			pageAddr = (vcom_rp[id].wrAddr+i*2048)/2048; 			

//			W25N01GV_WritePageAddr_Data(pWrBuf,0,pageAddr,2048);

		}

			return 0;

}

/*   Idle interrupt reception(SCI1)   */

/*For debug */

uint8_t Rx_Buffer_short[512] = {0}; //256

uint16_t Rx_Count_short = 0;

#include "dmac_drv.h"

#define Uart_Channel	2        //DMA channel

DMA_CHANNEL_REG *sci_dma_channel[2][DMAC_CHNUM] = {{(DMA_CHANNEL_REG *)(DMA1_BASE_ADDR ),(DMA_CHANNEL_REG *)(DMA1_BASE_ADDR + 0x58 ),

									(DMA_CHANNEL_REG *)(DMA1_BASE_ADDR + 0xB0 ),(DMA_CHANNEL_REG *)(DMA1_BASE_ADDR + 0x108)},

												   {(DMA_CHANNEL_REG *)(DMA2_BASE_ADDR ),(DMA_CHANNEL_REG *)(DMA2_BASE_ADDR + 0x58 ),

									(DMA_CHANNEL_REG *)(DMA2_BASE_ADDR + 0xB0 ),(DMA_CHANNEL_REG *)(DMA2_BASE_ADDR + 0x108)}};//global struct variable for for Channel registers

DMA_CONTROL_REG *sci_dma_control[2] = {(DMA_CONTROL_REG*)(DMA1_BASE_ADDR+0x2C0),

																				(DMA_CONTROL_REG*)(DMA2_BASE_ADDR+0x2C0)};//global struct variable for for DMAC registers

uint16_t dma_uartRX(UART_TypeDef *UARTx,uint8_t n, uint8_t *dest,uint32_t len)

{

	uint8_t dmaNum = 0;

	uint16_t ret = 0;

	uint16_t temp = 0;

	if(UARTx == SCI2)

	{

		dmaNum =1;

	}

	else					//SCI1 SCI3

	{

		dmaNum =0;

	}

	sci_dma_control[dmaNum]->DMA_CHEN &= (~(CHANNEL_WRITE_ENABLE(n)|CHANNEL_ENABLE(n)));////DMA disable

	sci_dma_control[dmaNum]->DMA_CONFIG = 0;

	sci_dma_channel[dmaNum][n]->DMA_SADDR = (uint32_t)&UARTx->SCIDRL;

	sci_dma_channel[dmaNum][n]->DMA_DADDR = (uint32_t)dest;

	sci_dma_channel[dmaNum][n]->DMA_CTRL = DIEC|SNOCHG|P2M_DMA;

	sci_dma_channel[dmaNum][n]->DMA_CTRL_HIGH =  len;

	sci_dma_control[dmaNum]->DMA_CONFIG = 1;

	sci_dma_channel[dmaNum][n]->DMA_CFG = (HS_SEL_SRC_HARD)|(HS_SEL_DST_SOFT)|(FIFO_EMPTY)|(CH_PRIOR2);

	if(UARTx == SCI1)

	{

		sci_dma_channel[dmaNum][n]->DMA_CFG_HIGH = (0xb<<7);

	}

	else if(UARTx == SCI2)

	{

		sci_dma_channel[dmaNum][n]->DMA_CFG_HIGH = (0x0<<7);

	}

	else

	{

		sci_dma_channel[dmaNum][n]->DMA_CFG_HIGH = (0xd<<7);

	}

	sci_dma_control[dmaNum]->DMA_CHEN |= (CHANNEL_WRITE_ENABLE(n)|CHANNEL_ENABLE(n));

	 return ret;

}

uint32_t DMA_uart_GetRecvLen(UART_TypeDef *UARTx,uint8_t n)

{

  uint8_t dmaNum = 0;

	if(UARTx == SCI2)

	{

		dmaNum =1;

	}

	else					//SCI1 SCI3

	{

		dmaNum =0;

	}

	return sci_dma_channel[dmaNum][n]->DMA_CTRL_HIGH;

}

void SCI1_DMA_Init(unsigned int pclk,unsigned int bound)

{

	uint32_t band_rate=0;

	NVIC_Init(0, 0, SCI1_IRQn, 2);

	SCI1->SCIBRDF=(((pclk*8/bound)+1)/2)&0x003f;

	band_rate =(pclk*4/bound)>>6;

	SCI1->SCIBDH  =(uint8_t)((band_rate>>8)&0x00ff);

	SCI1->SCIBDL  =(uint8_t)(band_rate&0x00ff);

	SCI1->SCICR1 &=~(1<<4);	//Data frame??1+8+1

	SCI1->SCICR1 &=~(1<<1);	//No verification

	SCI1->SCIRXTOCTR = 64;

	SCI1->SCIFCR = 0;

	SCI1->SCIFCR  |= (SCIFCR_RFEN|SCIFCR_RXFLSEL_1_8|SCIFCR_TXFLSEL_1_8);	//RX FIFOenable

	SCI1->SCIFCR2 |= (SCIFCR2_RXFCLR|SCIFCR2_RXFTOE);	//clean fifo , time over

	SCI1->SCICR1  |=  SCICR1_ILT_MASK; 					//Idle frame starts from end bit

	SCI1->SCICR2  |= (SCICR2_TE_MASK|SCICR2_RE_MASK|SCICR2_ILIE_MASK);	//Idle interrupt, receive, send enable

//	SCI3->SCICR2  |= SCICR2_RE_MASK;

	SCI1->SCIDCR |= SCIDCR_RXDMAE_MASK;	//Uart_DMA enable

	dma_uartRX(SCI1,Uart_Channel, Rx_Buffer_short,256);

}

void SCI3_DMA_Init(unsigned int pclk,unsigned int bound)

{

	uint32_t band_rate=0;

	NVIC_Init(0, 0, SCI3_IRQn, 2);

	SCI3->SCIBRDF=(((pclk*8/bound)+1)/2)&0x003f;

	band_rate =(pclk*4/bound)>>6;

	SCI3->SCIBDH  =(uint8_t)((band_rate>>8)&0x00ff);

	SCI3->SCIBDL  =(uint8_t)(band_rate&0x00ff);

	SCI3->SCICR1 &=~(1<<4);	//Data frame??1+8+1

	SCI3->SCICR1 &=~(1<<1);	//No verification

	SCI3->SCIRXTOCTR = 64;

	SCI3->SCIFCR = 0;

	SCI3->SCIFCR  |= (SCIFCR_RFEN|SCIFCR_RXFLSEL_1_8|SCIFCR_TXFLSEL_1_8);	//RX FIFOenable

	SCI3->SCIFCR2 |= (SCIFCR2_RXFCLR|SCIFCR2_RXFTOE);	//clean fifo , time over

	SCI3->SCICR1  |=  SCICR1_ILT_MASK; 					//Idle frame starts from end bit

	SCI3->SCICR2  |= (SCICR2_TE_MASK|SCICR2_RE_MASK|SCICR2_ILIE_MASK);	//Idle interrupt, receive, send enable

//	SCI3->SCICR2  |= SCICR2_RE_MASK;

	SCI3->SCIDCR |= SCIDCR_RXDMAE_MASK;	//Uart_DMA enable

	dma_uartRX(SCI3,Uart_Channel, Rx_Buffer_short,256);

}

void SCI1_IRQHandler(void)

{

	uint16_t tmp,ret;

	uint8_t clear_idle_flag;

	UART_TypeDef *UARTx=SCI1;

	//UART_Enter idle interrupt

	if(UARTx->SCISR1 & SCISR1_IDLE_MASK)      //The receiver is idle

	{			

			//Çå³ý±ê־λ

		while((UARTx->SCIFSR&SCIFSR_REMPTY_MASK) == 0) //FIFO not empty, Wait for the received data to be transmitted to DMA

		{

			if( UARTx->SCIFSR& (SCIFSR_RFULL_MASK|SCIFSR_RTOS_MASK) )  //FIFO overflow??receive time-out

			{

				break;

			}

		}

		tmp = UARTx->SCIDRL;

		UARTx->SCIFCR2 |= SCIFCR2_RXFCLR;

		Rx_Count_short = DMA_uart_GetRecvLen(UARTx,Uart_Channel);

//		gUsartRx.Flag = 1;

		printf("len:%d\r\n",Rx_Count_short);

	//	SCI3->SCICR2  |= SCICR2_RE_MASK;

	//	SCI3->SCIDCR |= SCIDCR_RXDMAE_MASK;	//Uart_DMA enable

//		for(unsigned char i = 0 ; i < Rx_Count_short;i++ )

//		{

//				printf(" %x ",Rx_Buffer_short[i]);

//		}

		number++;

		dma_uartRX(UARTx,Uart_Channel, Rx_Buffer_short,256);

		ota_lt7689_flag=1;

				clear_idle_flag	=	SCI1->SCIDRL;

				clear_idle_flag	= SCI1->SCISR1;

	}

}

void SCI3_IRQHandler(void)

{

	uint16_t tmp,ret;

	uint8_t clear_idle_flag;

	UART_TypeDef *UARTx=SCI3;

	//UART_Enter idle interrupt

	if(UARTx->SCISR1 & SCISR1_IDLE_MASK)      //The receiver is idle

	{			

			//Çå³ý±ê־λ

		while((UARTx->SCIFSR&SCIFSR_REMPTY_MASK) == 0) //FIFO not empty, Wait for the received data to be transmitted to DMA

		{

			if( UARTx->SCIFSR& (SCIFSR_RFULL_MASK|SCIFSR_RTOS_MASK) )  //FIFO overflow??receive time-out

			{

				break;

			}

		}

		tmp = UARTx->SCIDRL;

		UARTx->SCIFCR2 |= SCIFCR2_RXFCLR;

		Rx_Count_short = DMA_uart_GetRecvLen(UARTx,Uart_Channel);

//		gUsartRx.Flag = 1;

		printf("len:%d\r\n",Rx_Count_short);

	//	SCI3->SCICR2  |= SCICR2_RE_MASK;

	//	SCI3->SCIDCR |= SCIDCR_RXDMAE_MASK;	//Uart_DMA enable

//		for(unsigned char i = 0 ; i < Rx_Count_short;i++ )

//		{

//				printf(" %x ",Rx_Buffer_short[i]);

//		}

		number++;

		dma_uartRX(UARTx,Uart_Channel, Rx_Buffer_short,256);

		ota_lt7689_flag=1;

				clear_idle_flag	=	SCI1->SCIDRL;

				clear_idle_flag	= SCI1->SCISR1;

	}

}